16.5 Analog – Digital Conversion

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Data-acquisition systems in machine condition monitoring, fault detection and diagnosis, and vibration

testing employ digital computers for various tasks including signal processing, data analysis and

reduction, parameter identification, and decision making. Typically, the measured response (output) of a

dynamic system is available in the analog form as a continuous signal (function of continuous time).

Furthermore, typically, the excitation signals (inputs) for a dynamic system have to be provided in the

analog form.

Inputs to a digital device, say from a digital computer, and outputs from a digital device are necessarily

present in the digital form. Hence, when a digital device is interfaced with an analog device, the interface

hardware and associated driver software must perform several important functions. Two of the most

important interface functions are digital-to-analog conversion (DAC) and analog-to-digital conversion

(ADC). A digital output from a digital device has to be converted into the analog form for it to be fed into

an analog device such as actuator or analog recording or display unit. Also, an analog signal has to be

converted into the digital form according to an appropriate code before it is read by a digital processor or

computer. Digital-to-analog converters are simpler and lower in cost than analog-to-digital converters.

Furthermore, some types of analog-to-digital converters employ a digital-to-analog converter to perform

their function. For these reasons, we will first discuss DAC.

16.5.1 Digital-to-Analog Conversion

The function of a DAC is to convert a sequence of digital words stored in a data register (called a DAC

register), typically in straight binary form, into an analog signal. The data in the DAC register may come

from a data bus of a computer. Each binary digit (bit) of information in the register may be present as a

state of a bistable (two-stage) logic device, which can generate a voltage pulse or a voltage level to

represent that bit. For example, the off state of a bistable logic element, the absence of a voltage pulse, a

low level of a voltage signal, or no change in a voltage level can represent binary 0. Then, the on state of a

bistable device, the presence of a voltage pulse, a high level of a voltage signal, or a change in a voltage level

will represent binary 1. The combination of these bits, which form the digital word in the DAC register,

will correspond to some numerical value for the output signal. The purpose of DAC is to generate an

output voltage (signal level) that has this numerical value and maintain the value until the next digital

word is converted. Since a voltage output cannot be arbitrarily large or small, for practical reasons, some

form of scaling will have to be employed in the DAC process. This scale will depend on the reference

voltage, vref, used in the particular DAC circuit.

A typical DAC unit is an active circuit in the IC form, which may consist of a data register (digital

circuits), solid-state switching circuits, resistors, and operational amplifiers powered by an external

power supply that can provide a reference voltage. The reference voltage will determine the maximum

value of the output ( full-scale voltage). An IC chip that represents the DAC is usually one of many

components mounted on a printed circuit (PC) board. This PC board may be identified by several names

including input/output (I/O) board, I/O card, interface board, and data acquisition and control board.

Typically, the same board will provide both DAC and ADC capabilities for many output and input

channels.

There are many types and forms of DAC circuits. The form will depend mainly on the manufacturer,

the requirements of the user, or of the particular application. Most DACs are variations of two basic

types: the weighted (or summer or adder) type and the ladder type. The latter type of DAC is more

desirable, though the former can be somewhat simpler and less expensive.

16.5.1.1 DAC Error Sources

For a given digital word, the analog output voltage from a DAC is not exactly equal to what is given by the

analytical formulas. The difference between the actual output and the ideal output is the error. The DAC

error can be normalized with respect to the full-scale value.

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There are many causes of DAC error. Typical error sources include parametric uncertainties and

variations, circuit time constants, switching errors, and variations and noise in the reference voltage.

Several types of error sources and representations are discussed below.

1. Code ambiguity: In many digital codes (for example, in the straight binary code), incrementing a

number by a least significant bit (LSB) will involve more than one bit-switching. If the speed of

switching from 0 to 1 is different from that for 1 to 0, and if switching pulses are not applied to the

switching circuit simultaneously, the bit-switchings will not take place simultaneously. For

example, in a 4-bit DAC, incrementing from decimal 2 to decimal 4 will involve changing the

digital word from 0011 to 0100. This requires two bit-switchings from 1 to 0 and one bit-switching

from 0 to 1. If 1 to 0 switching is faster than the 0 to 1 switching, then an intermediate value given

by 0000 (decimal 0) will be generated, with a corresponding analog output. Hence, there will be a

momentary code ambiguity and associated error in the DAC signal. This problem can be reduced

(and eliminated in single bit increments) if a gray code is used to represent the digital data.

Improved switching circuitry will also help reduce this error.

2. Settling time: The circuit hardware in a DAC unit will have some dynamics, with associated time

constants and perhaps oscillations (underdamped response). Hence, the output voltage cannot

instantaneously settle to its ideal value upon switching. The time required for the analog output to

settle within a certain band (say ^ 2% of the final value or ^ 1/2 resolution), following the

application of the digital data, is termed settling time. Naturally, settling time should be smaller for

better (faster and more accurate) performance. As a guideline, the settling time should be

approximately half the data arrival time. Note that the data arrival time is the time interval

between the arrival of two successive data values, and is given by the inverse of the data arrival rate.

3. Glitches: Switching of a circuit will involve sudden changes in magnetic flux due to current

changes. This will induce voltages that produce unwanted signal components. In a DAC circuit,

these induced voltages due to rapid switching can cause signal spikes that will appear in the

output. The error due to these noise signals is not significant at low conversion rates.

4. Parametric errors: Resistor elements in a DAC might not be precise, particularly when resistors

within a wide range of magnitudes are employed, as in the case in a weighted-resistor DAC. These

errors appear in the analog output. Furthermore, aging and environmental changes (primarily,

change in temperature) will change the values of circuit parameters, resistance in particular. This

also will result in DAC error. These types of error, which are due to the imprecision of circuit

parameters and variations of parameter values, are termed parametric errors. Effects of such errors

can be reduced by several ways, including the use of compensation hardware (and perhaps

software) and directly, by using precise and robust circuit components and employing good

manufacturing practices.

5. Reference voltage variations: Since the analog output of a DAC is proportional to the reference

voltage, vref ; any variations in the voltage supply will directly appear as an error. This problem can

be overcome by using stabilized voltage sources with sufficiently low output impedance.

6. Monotonicity: Clearly, the output of a DAC should change by its resolution ðdy ¼ vref =2nÞ for each

step of one LSB increment in the digital value. This ideal behavior might not exist in some real

DACs due to errors such as those mentioned above. At least the analog output should not decrease

as the value of the digital input increases. This is known as the monotonicity requirement that

should be met by a practical DAC.

7. Nonlinearity: Suppose that the digital input to a DAC is varied from ½0 0…0􀀉 to ½1 1…1􀀉 in

steps of one LSB. Ideally the analog output should increase in constant jumps of dy ¼ vref =2n;

giving a staircase-shaped analog output. If we draw the best linear fit for this ideally montonic

staircase response, it will have a slope equal to the resolution/step. This slope is known as the

ideal scale factor. Nonlinearity of a DAC is measured by the largest deviation of the DAC

output from this best linear fit. Note that, in the ideal case, the nonlinearity is limited to half

the resolution ð1=2Þdy:

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One cause of nonlinearity is clearly the faulty bit-transitions. Another cause is circuit nonlinearity in

the conventional sense. Specifically, owing to nonlinearities in circuit elements such as opamps and

resistors, the analog output will not be proportional to the value of the digital word dictated by the bitswitchings

(faulty or not). This latter type of nonlinearity can be accounted for by using calibration.

16.5.2 Analog-to-Digital Conversion

Analog signals, which are continuously defined with respect to time, have to be sampled at discrete time

points and the sample values have to be represented in the digital form (according to a suitable code) to

be read into a digital system such as a microcomputer. An ADC is used to accomplish this. For example,

since response measurements of dynamic systems are usually available as analog signals, these signals

have to be converted into the digital form before passing on to a signal analysis computer. Hence, the

computer interface for the measurement channels should contain one or more ADCs.

DACs and ADCs are usually situated on the same digital interface board. However, the ADC process is

more complex and time consuming than the DAC process. Furthermore, many types of ADCs use DACs

to accomplish the analog-to-digital conversion. Hence, ADCs are usually more costly than and their

conversion rate is usually slower than that of DACs. Several types of ADCs are commercially available.

The principle of operation varies depending on the type.

16.5.3 Analog-to-Digital Converter Performance Characteristics

For ADCs that use a DAC internally, the same error sources that were discussed previously for DACs

apply. Code ambiguity at the output register is not a problem because the converted digital quantity is

transferred instantaneously to the output register. Code ambiguity in the DAC register can still cause

error in ADCs that use a DAC. Conversion time is a major factor as it is much larger for an ADC. In

addition to resolution and dynamic range, quantization error will be applicable to an ADC. These

considerations that govern the performance of an ADC are discussed below.

16.5.3.1 Resolution and Quantization Error

The number of bits, n; in an ADC register determines the resolution and dynamic range of the ADC. For

an n-bit ADC, the output register size is n bits. Hence, the smallest possible increment of the digital

output is one LSB. The change in the analog input that results in a change of one LSB at the output is the

resolution of the ADC. The range of digital outputs is from 0 to 2n 2 1 for the unipolar (unsigned) case.

This represents the dynamic range. Hence, as for a DAC, the dynamic range of an n-bit ADC is given by

the ratio

DR ¼ 2n 2 1 ð16:62Þ

or, in decibels

DR ¼ 20 log10ð2n 2 1Þ dB ð16:63Þ

The full-scale value of an ADC is the value of the analog input that corresponds to the maximum digital

output.

Suppose that an analog signal within the dynamic range of the ADC is converted. Since the analog

input (sample value) has infinitesimal resolution and the digital representation has a finite resolution

(one LSB), an error is introduced in the ADC process. This is known as the quantization error. A digital

number increments in constant steps of 1 LSB. If an analog value falls at an intermediate point within a

single-LSB step, then there is a quantization error. Rounding of the digital output can be accomplished as

follows. The magnitude of the error when quantized up is compared with that when quantized down,

say, using two hold elements and a differential amplifier. Then, we retain the digital value corresponding

to the lower error magnitude. If the analog value is below the 1/2 LSB mark, then the corresponding

digital value is represented by the value in the beginning of the step. If the analog value is above the 1/2

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LSB mark, then the corresponding digital value is the value at the end of the step. It follows that, with this

type of rounding, the quantization error does not exceed 1/2 LSB.

16.5.3.2 Monotonicity, Nonlinearity, and Offset Error

Considerations of monotonicity and nonlinearity are important for an ADC as well as for a DAC. The

input is an analog signal and the output is digital in the case of ADC. Disregarding quantization error, the

digital output of an ADC will increase in constant steps in the shape of an ideal staircase when the analog

input is increased from zero in steps of the device resolution ðdyÞ: This is the ideally monotonic case. The

best straight-line fit to this curve has a slope equal to 1=dy (LSB/V). This is the ideal gain or ideal scale

factor. However, there will still be an offset error of 1/2 LSB because the best linear fit will not pass through

the origin. Adjustments can be made for this offset error.

Incorrect bit-transitions can take place in an ADC due to various errors that might be present and due

to circuit malfunctions. The best linear fit under such faulty conditions will have a slope different from

the ideal gain. The difference is the gain error. Nonlinearity is the maximum deviation of the output from

the best linear fit. It is clear that, with perfect bit transitions, in the ideal case, a nonlinearity of 1/2 LSB

will be present. Nonlinearities larger than this result from incorrect bit-transitions. As in the case of DAC,

another source of nonlinearity in an ADC is the existence of circuit nonlinearities that would deform the

analog input signal before being converted into the digital form.

16.5.3.3 Analog-to-Digital Converter Conversion Rate

It is clear that ADC is much more time consuming than DAC. The conversion time is a very important

factor because the rate at which conversion can take place governs many aspects of data acquisition,

particularly in real-time applications. For example, the data sampling rate has to synchronize with the

ADC conversion rate. This, in turn, will determine the Nyquist frequency (half the sampling rate) which

is the maximum value of useful frequency present in the sampled signal. Furthermore, the sampling rate

will dictate storage and memory requirements. Another important consideration related to the ADC

conversion rate is the fact that a signal sample must be maintained at that value during the entire process

of conversion into the digital form. This requires a hold circuit and this circuit should be able to perform

accurately at the largest possible conversion time for the particular ADC unit.

The total time taken to convert an analog signal will depend on other factors besides the time taken for

conversion from sampled data to digital data. For example, in multiple-channel data acquisition, the time

taken to select the channel has to be counted. Furthermore, time needed to sample the data and time

needed to transfer the converted digital data into the output register have to be included. The conversion

rate for an ADC is the inverse of the overall time needed for a conversion cycle. Typically, however,

conversion rate depends primarily on the bit conversion time in the case of one comparison-type

ADC and on the integration time in the case of an integration-type ADC. A typical time period for a

comparison step or counting step in an ADC is Dt ¼ 5 msec: Hence, for an eight-bit successiveapproximation

ADC the conversion time is 40 msec: The corresponding sampling rate is in the order of

(less than) 1=40 £ 1026 ¼ 25 £ 103 samples=sec (or 25 kHz). The maximum conversion rate for an eightbit

counter ADC is about 5 £ ð28 2 1Þ ¼ 1275 msec: The corresponding sampling rate would be of the

order of 780 samples/sec. Note that this is considerably slow. The maximum conversion time for a dualslope

ADC can be still larger (slower).

16.5.4 Sample-and-Hold Circuitry

In typical applications of data acquisition that use ADC, the analog input to ADC can be very transient.

Furthermore, ADC is not instantaneous (conversion time is much larger than the DAC time).

Specifically, the incoming analog signal might be changing at a rate higher than the ADC conversion rate.

Then, the input signal value will vary during the conversion period and there will be an ambiguity as to

the input value corresponding to a digital output value. Hence, it is necessary to sample the analog input

signal and maintain the input to the ADC at this value until the ADC is completed. In other words,

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since we are typically converting analog signals that can vary at a high speed, it is often necessary to

sample and hold (S/H) the input signal for each ADC cycle. Each data sample must be generated and

captured by the S/H circuit on the issue of the “start conversion” (SC) control signal, and the captured

voltage level has to be maintained constant until the “conversion complete” (CC) control signal is issued

by the ADC unit.

The main element in an S/H circuit is the holding capacitor. A schematic diagram of a S/H circuit is

shown in Figure 16.16. The analog input signal is supplied through a voltage follower to a solid-state

switch. The switch typically uses a field-effect transistor (FET), such as the metal-oxide semiconductor

field effect transistor (MOSFET).

The switch is closed in response to a “sample pulse” and is opened in response to a “hold pulse.” Both

control pulses are generated by the control logic unit of the ADC. During the time interval between these

two pulses, the holding capacitor is charged to the voltage of the sampled input. This capacitor voltage is

then supplied to the ADC through a second voltage follower.

The functions of the two voltage followers are now explained. When the FET switch is closed in

response to a sample command (pulse), the capacitor must be charged as quickly as possible. The

associated time constant (charging time constant) tc is given by

tc ¼ RsC ð16:64Þ

in which

Rs ¼ source resistance

C ¼ capacitance of the holding capacitor

Since tc must be very small for fast charging and, since C is fixed by the holding requirements (typically

C is of the order of 100 pF where 1 pF ¼ 1 £ 10212 F), we need a very small source resistance. The

requirement is met by the input voltage follower (which is known to have a very low output impedance),

thereby providing a very small Rs: Furthermore, since a voltage follower has a unity gain, the voltage at

the output of this input voltage follower is equal to the voltage of the analog input signal, as required.

Next, once the FET switch is opened in response to a hold command (pulse), the capacitor should not

discharge. This requirement is met due to the presence of the output voltage follower. Since the input

impedance of a voltage follower is very high, the current through its leads is almost zero. Because of this,

the holding capacitor has a virtually zero discharge rate under hold conditions. Furthermore, we like the

output of this second voltage follower to be equal to the voltage of the capacitor. This condition is also

satisfied due to the fact that a voltage follower has a unity gain. Hence, the sampling will be almost

instantaneous and the output of the S/H circuit will be maintained (almost) constant during the holding

period due to the presence of the two voltage followers. Note that the practical S/H circuits are zero-orderhold

devices by definition.

Solid-State

(FET) Switch

Voltage

Follower

(Low Zout)

Analog

Input

S/H Output

(Supply to ADC)

C

Voltage

Follower

(High Zin)

Holding

Capacitor

Sampling Rate

Control (Timing)

FIGURE 16.16 A sample and hold circuit.

Signal Conditioning and Modification 16-41

© 2005 by Taylor & Francis Group, LLC

16.5.5 Digital Filters

A filter is a device that eliminates undesirable frequency components in a signal and passes only the

desirable frequency components through. In analog filtering, the filter is a physical, dynamic system,

typically an electric circuit. The signal to be filtered is applied (input) to this dynamic system. The output

of the dynamic system is the filtered signal. It follows that any physical dynamic system can be interpreted

as an analog filter.

An analog filter can be represented by a differential equation with respect to time. It takes an analog

input signal, uðtÞ; that is defined continuously in time, t; and generates an analog output, yðtÞ: A digital

filter is a device that accepts a sequence of discrete input values (say, sampled from an analog signal at

sampling period Dt).

{uk} ¼ _____________{u0; u1; u2; …} ð16:65Þ

and generates a sequence of discrete output values:

{yk} ¼ {y0; y1; y2; …} ð16:66Þ

Hence, a digital filter is a discrete-time system and it can be represented by a difference equation.

An nth order linear difference equation can be written in the form

a0yk þ a1yk21 þ · · · þ anyk2n ¼ b0uk þ b1uk21 þ · · · þ bmuk2m ð16:67Þ

This is a recursive algorithm in the sense that it generates one value of the output sequence using previous

values of the output sequence and all values of the input sequence up to the present time point. Digital

filters represented in this manner are termed recursive digital filters. There are filters that employ digital

processing, in which a block (a collection of samples) of the input sequence is converted in a one-shot

computation into a block of the output sequence. Such filters are not recursive filters. Nonrecursive filters

usually employ digital Fourier analysis, the FFT algorithm in particular. We restrict our discussion below

to recursive digital filters. Our intention in the present section is to give a brief (and nonexhaustive)

introduction to the subject of digital filtering.

16.5.5.1 Software Implementation and Hardware Implementation

In digital filters, signal filtering is accomplished through digital processing of the input signal. The

sequence of input data (usually obtained by sampling and digitizing the corresponding analog signal) is

processed according to the recursive algorithm of the particular digital filter. This generates the output

sequence. This digital output can be converted into an analog signal using a DAC if so desired.

A recursive digital filter is an implementation of a recursive algorithm that governs the particular

filtering (e.g., low-pass, high-pass, band-pass, and band-reject). The filter algorithm can be implemented

either by software or by hardware. In software implementation, the filter algorithm is programmed into a

digital computer. The processor (e.g., the microprocessor) of the computer can process an input data

sequence according to the run-time filter program stored in the memory (in machine code) to generate

the filtered output sequence.

Digital processing of data is accomplished by means of logic circuitry that can perform basic arithmetic

operations such as addition. In the software approach, the processor of a digital computer makes use of

these basic logic circuits to perform digital processing according to the instructions of a software program

stored in the computer memory. Alternatively, a hardware digital processor can be put together to

perform a somewhat complex, yet fixed, processing operation. In this approach, the program of

computation is said to be in hardware. The hardware processor is then available as an IC chip whose

processing operation is fixed and cannot be modified. The logic circuitry in the IC chip is designed to

accomplish the required processing function. Digital filters implemented by this hardware approach are

termed hardware digital filters.

The software implementation of digital filters has the advantage of flexibility; the filter algorithm can

be easily modified by changing the software program that is stored in the computer. If, on the other hand,

a large number of filters of a particular (fixed) structure are needed commercially, then it is economical to

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design the filter as an IC chip and replicate the chip in mass production. In this manner, very low-cost

digital filters can be produced. A hardware filter can operate at a much faster speed than a software filter

because, in the former case, processing takes place automatically through logic circuitry in the filter chip

without having to access the processor, a software program, and various data items stored in the memory.

The main disadvantage of a hardware filter is that its algorithm and parameter values cannot be modified,

and the filter is dedicated to a fixed function.

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